What is the difference between Pmos and Nmos Transistors?

A metal-oxide-semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (SiO2) and a layer of metal (polycrystalline silicon is actually used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a plane capacitor, with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of holes), a positive VGB ( gate base voltage) tends to reduce the concentration of holes and increase the concentration of electrons. If VGB is high enough, the concentration of negative charge carriers near the gate is more than that of positive charges, in what is known as an inversion layer.

This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.

PMOS (′pē′mös) :

(electronics) Metal-oxide semiconductors that are made on n-type substrates, and whose active carriers are holes that migrate between p-type source and drain contacts. Derived from p-channel metal-oxide semiconductor.

NMOS (′en′mös)

(electronics) Metal-oxide semiconductors that are made on p-type substrates, and whose active carriers are electrons that migrate between n-type source and drain contacts. Derived from n-channel metal-oxide semiconductor.

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NMOS:

nMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

As an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:

A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

While nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with nMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS logic gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.

Also, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.

Additionally, the asymmetric input logic levels make nMOS circuits susceptible to noise.

These disadvantages are why nMOS logic was supplanted by CMOS logic both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.

PMos:

Full details on:

http://www.kettering.edu/~bguru/mosfets/PMOS-INT.p...

For more info go to :

http://www.faqs.org/docs/electric/Semi/SEMI_6.html

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What is the difference between Pmos and Nmos Transistors?

Nmos And Pmos