Question about MIPS?

This is not a very good problem.  The fourth instruction can't get past the register operand fetch stage (normally very early in the pipeline) until the first instruction finished storing the result of the memory load into the $6 register (normally one of the last stages in the pipeline.)

I suppose you are intended to assume each pipelined instruction takes all 15 stages, with each starting one clock cycle after the previous instruction.  The whole sequence is done when the last instruction finishes.  It start 4 clocks after the first instruction and finishes 15 clocks later.  Total time 19*0.6ns.

The nonpipelined version took 3.5ns * 5.  Compute and compare.

That's over-simplified, I think.  It doesn't account for wait states (some processors don't have those, depending on compilers to reorder instructions or insert "no operation" instructions to make sure a register isn't accessed before the intended value has arrived.)  It also doesn't account for completion of previous instructions in the pipeline, nor for partial execution of future instructions as the final sub instruction finishes.

But the problem doesn't say how you are expected to measure the pipelined instruction time.  So I guessed.  Like I said, it's not a very good problem.