Why is 11 an illegal input to an SR latch or flipflop? Digital Logic Electrical Engineering?

An SR is a set-reset latch. Let's assume all positive logic...

The initial condition is 0 to the set input (S), and 0 to the reset (R). in this condition, the output is 0. Now, we put a high or 1 into the set (S) input. The output then goes high (to 1). If the S input falls to 0, the output stays at 1, therefore, it is latched. If we want to bring the output low again, we must use the reset (R) input. By placing a 1 on the R input, we reset the output to 0.

So, what happens at the output when you put a 1 on the S input, and also have a 1 at the R input? Well, that condition is undefined, because the input at S is trying to drive the output to a 1, while the input at R is trying to drive the output to a 0.

In reality, some SR latches may actually exhibit a defined output state for this condition, but in terms of pure logic, it is undefined.

Hope that explains it.

Do not make this any more difficult than necessary - A register simply holds a logic bit, whether it be a "1" or a "0" There are two fundamental storage devices - Flip Flops and Latches. Either one will hold the data until an event happens (usually a clock) Latches work on logic levels, and captures the logic prior to the logic going to an opposite state. Flip Flop works on edges (usually of clocks) and captures the data on the rising or falling edge of the clock. You can get into all the hold time and set up issues; but the flip flop (usually called a Delay or D-FlipFlop) is the most fundamental memory concept.

Feeding an SR flip flop 1 1 is the same as driving your car with the brake and gas on at the same time - it causes conflict.

11 means that the 'set' input S=1 and the 'reset' input R=1.

This is considered illegal because it leaves an indeterminate state. The flip flop doesn't know whether it should be 'set' or 'reset', and we can't be sure what output may result.