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The CS stage depicted in figure below, must achieve a voltage gain AV of 15 at a bias current Id = 0.4 mA. If?
The CS stage depicted in figure below, must achieve a voltage gain AV of 15 at a bias current Id = 0.4 mA. If λ1= 0.17V-1 and λ2 = 0.08V-1, determine the required value of W2 in nano meter when L is 90nm.Assume Vdd = 1.1V, µn*cox = 151µVA/V2 , µp*cox = 73µVA/V2 and Vth = 338mV.
Keep answer up to 3 decimal places
the circuit is
pmos on top of nmos vout is between.... the 2 vbias on gate of nmos and vdd on gate of pmos
i want to check my answer....
